Instruction Set Architecture

Program Status Word

Program Status Upper

The PSU primarily contains the Stack Pointer SP for the internal stack as well as the global Interrupt Inhibit II. The pointer increments when values are pushed onto the stack and decrements when values are popped. It always points to where the next value will go, so the TOS is actually at SP - 1.

This register also contains the bits that control the two digital input/output lines Sense and Flag. The F bit sets the state (high or low) of Flag and the current state of the Sense input can be read out of the F bit.

Bit 4 of the PSU is not wired up to any hardware functionality, but is physically present and can be read and writen by a user program.

The PSU is reset to 20h on reset, meaning the II bit is set.

Program Status Lower

The PSL contains all processor flags and settings.

C is the carry flag defined by arithmatic operations.

COM is a processor setting that modifies the behavior of the compare instructions. If clear, they will compare values as two’s-complement signed bytes. If set, they will compare values as unsigned bytes.

OVF if set, indicates that the last addition or subtraction operation resulted in an arithmatic overflow, meaning the result could not be represented by a signed byte.

WC is a processor setting that modifies the behavior of addition and subtraction instructions, as well as left- and right-rotate.

IDC is the Interdigit Carry, that is the carry from bit 3 to bit 4 during an addition, subtraction of bitshift operation. It is used in combination with the dar instruction to perform arithmatic on packed BCD values.

CC is the Condition Code. This code is set either by any instruction that modifies a general purpose register (unless otherwise specified) and compare and bit-test instructions. This code can be tested by software or conditional branch instructions.

This PSL is initialized to 0 on reset.

Unless otherwise specified, any instruction listed in this documentation that is described as affecting CC will do according to the new value in whichever register it modifies as listed in this table:

The value 11 will never be generated in the CC by any instruction.

Implied

The instruction consists only of a 8-bit opcode. All operands are implied.

Register Addressing

All instructions that operate on a single register in-place are encoded in a single byte with a 6-bit opcode and 2-bit register index.

Zero Addressing

This is a special form of Register Addressing that is identical in encoding but operates on a pair of registers, the second of which is always implied to be R0.

With the exception of strz or unless otherwise specified, R0 is also the destination for the instruction result with the specified register index only used as a source.

Immediate Addressing

Immediate addressed instructions operate on a register and immediate value. The operation and register are encoded as in Register Addressing and followed by a second byte containing the immediate value.

Relative Addressing

Relative addressed instructions are either branch instructions or memory reference instructions, in which case they load or store one byte in memory as part of their operation. Relative instructions reference a memory location relative to the current Program Counter value. The second byte contains a signed 7-bit displacement value that is added to the Program Counter to obtain the effective address.

Indirect addressing may additionally be specified.

There are some exceptions (zbsr, zbrr) where the effective address is computed not as relative to the Program Counter, but as relative to address 0, page 0.

This mode applies the same to branch or memory reference instructions.

Absolute Addressing for non-branch instructions

Absolute addressed instructions encode a complete 13-bit page-relative address in the two bytes following the opcode and register index. This immediate address is the effective address.

Indirect and/or indexed addressing may additionally be specified.

Absolute Addressing for branch instructions

Absolute addressing for branch instructions differs from regular absolute addressing, not allowing for indexed addressing (but still allowing indirect addressing).

These instructions encode a 15-bit address as the branch target, corresponding to the entire PC and the 2 least-significant bits of Page Control. The most significant bit of Page Control is unchanged.

Additionally, the register index may instead be a Condition Code Mask for conditional branches.

Far / Far Indirect addressing

Far and Far Indirect addressing modes were added in the AS2650v2 to extend the available total address space to 65,536 bytes, as well as make working with the paged memory layout easier.

These instructions encode a full 16-bit address. Unlike the other addressing modes, wether indirect addressing is specified is encoded in the opcode.

This mode applies the same to branch or memory reference instructions.

Indirect Addressing

Indirect Addressing may be specified on top of another addressing mode, when supported, by setting the I bit. When specified, the original effective address of the instruction is no longer the true memory reference. Instead, two successive bytes are read from this location which become the new effective address for the memory reference.

Essentially, this mode implements a pointer dereference. The pointer is stored in big endian format.

Indexed Addressing

Indexed Addressing may be specified on top of another addressing mode, when supported, by setting the Index Control bits to a value other than zero. Once enabled, the register index in the first instruction byte instead specifies which register to use for indexing. The operation’s actual register index implicitly becomes R0.

The current value of the register chosen for indexing is added onto the original effective address to obtain the new effective address.

If autoincrement or autodecrement are specified, the index register’s value is incremented or decremented before the address calculation.

Indexed and Indirect Addressing may both be supported on the same instruction. They are not mutually exclusive. If both are specified, the Indirect Addressing takes precedence and the pointer is read from memory and the index added onto it.

Extended Instructions

The AS2650v2 contains a series of extended instructions marked by a prefix, B7h. If the processor encounters this opcode, it will skip it and interpret the following byte(s) as an extended instruction. Besides this prefix, extended instructions follow the same rules for their addressing modes.

lodz/lodi/lodr/loda - Load Register value

These instructions transfer a byte of data into one of the general purpose registers. The source of the value may be another register, an immediate or a memory reference.

Affected flags: CC

eorz/eori/eorr/eora - Logical Exclusive OR

These instructions perform an exclusive OR logic operation on the bits of both operands.

Affected flags: CC

andz/andi/andr/anda - Logical AND

These instructions perform a AND logic operation on the bits of both operands.

Affected flags: CC

Note: the combination of r == 0 and m == 0 (andz,r0) is invalid. This opcode is used for a different instruction.

iorz/iori/iorr/iora - Logical Inclusive OR

These instructions perform a OR logic operation on the bits of both operands.

Affected flags: CC

addz/addi/addr/adda - Addition

These instructions perform an arithmatic addition on both operands. If the WC bit in the PSL is set, the carry flag C is also added onto the result.

The carry flag will be set to the carry out of the addition. The interdigit carry will be set to the carry from bit 3 to bit 4. The overflow flag is set if a signed overflow occured.

Affected flags: CC, C, IDC, OVF

subz/subi/subr/suba - Subtraction

These instructions perform an arithmatic subtraction of one operand from the other. If the WC bit in the PSL is set, the inverse of the carry flag C is also subtracted from the result.

In the case of Zero Addressing, the subtrahend is the value of the register determined by the register index. In the case of Immediate Addressing or a memory reference addressing, the subtrahend is the immediate or value from memory.

Internally, this operation forms the binary complement subtrahend and adds it onto the minuend, and also adds either one (WC == 0) or the carry flag (WC == 1).

The carry flag will be set to the carry out of this addition. The interdigit carry will be set to the carry from bit 3 to bit 4. The overflow flag is set if a signed overflow occured.

Affected flags: CC, C, IDC, OVF

strz/strr/stra - Store Register Value

These instructions store a register value to another register or memory. Immediate Addressing or a combination of r == 0 and m == 0 may not be specified. These opcodes are used for other instructions.

The CC is not affected unless m == 0 (Zero Addressing), in which case it is affected as normal based on the stored value. In Zero Addressing, the value of R0 is copied into another register.

comz/comi/comr/coma - Compare Values

These instructions compare two values from registers or memory and set the Condition Code according to the following tables. No registers or memory values are modified, only the comparison takes place.

If Zero Addressing is used:

Otherwise, where V is the byte loaded by the memory reference:

The comparison can be either signed or unsigned as set by the COM bit in PSL (signed if COM == 0, unsigned if COM == 1).

Affected flags: CC

bctr/bcta - Branch on Condition True

These instructions affect a relative or absolute branch only if the Condition Code matches the mask in the opcode, or the mask is equal to 11, which always affects an unconditional branch.

In the instruction mnemonic, the mask value can either be defined explicitely, eg. bcta,2 [target] or according to the following syntax:

eg. bctr,eq [target]

Affected flags: none

bstr/bsta - Branch to Subroutine on Condition True

These instructions behave identically to bctr/bcta explained above, except that they additionally push a return address onto the internal stack if the branch is taken. This address is a complete Instruction Pointer and will always point to the instruction immediatly following the branch.

Affected flags: none

brnr/brna - Branch if Not Zero

These instructions test the specified general purpose register’s value and only affect a branch if it is not zero. The register value is not modified.

Affected flags: none

bsnr/bsna - Branch to Subroutine if Not Zero

These instructions behave identically to brnr/brna explained above, except that they additionally push a return address onto the internal stack if the branch is taken. This address is a complete Instruction Pointer and will always point to the instruction immediatly following the branch.

Affected flags: none

bcfr/bcfa - Branch on Condition False

These instructions affect a relative or absolute branch only if the Condition Code does not match the mask in the opcode.

In the instruction mnemonic, the mask value can either be defined explicitely, eg. bcfa,2 [target] or according to the following syntax:

eg. bcfr,eq [target]

The CC mask may not be equal to 3. Those opcodes are used by other instructions.

Affected flags: none

bsfr/bsfa - Branch to Subroutine on Condition False

These instructions behave identically to bcfr/bcfa explained above, except that they additionally push a return address onto the internal stack if the branch is taken. This address is a complete Instruction Pointer and will always point to the instruction immediatly following the branch.

The CC mask may not be equal to 3. Those opcodes are used by other instructions.

Affected flags: none

birr/bira - Branch on Incrementing Register Not Zero

These instructions first increment the specified register, then affect a branch only if the new register value is not equal to zero.

Affected flags: none

bdrr/bdra - Branch on Decrementing Register Not Zero

These instructions first decrement the specified register, then affect a branch only if the new register value is not equal to zero.

Affected flags: none

retc - Return on Condition True

These instructions affect a subroutine return if the Condition Code matches the mask in the opcode. When true, a value is popped off of the internal stack and used to load the Page Control and Program Counter to become the new Instruction Pointer.

Affected flags: none

rete - Return on Condition True and Enable Interrupts

These instructions affect a subroutine return if the Condition Code matches the mask in the opcode. When true, a value is popped off of the internal stack and used to load the Page Control and Program Counter to become the new Instruction Pointer.

Additionally, the Interrupt Inhibit bit in the PSU is cleared, enabling interrupts globally.

Affected flags: II

rrr - Rotate Register Right

These instructions perform a right-rotate on the specified register in-place. The exact operation depends on the state of the WC flag in the PSL.

If WC is clear, the register is right-rotated and the Carry and Interdigit Carry are not changed. Bit 7 of the new register value is set from Bit 0 of the previous value.

If WC is set, the register is right-rotated through the Carry. The previous Carry is shifted into bit 7 of the result and the previous bit 0 becomes the next Carry. Additionally, the Interdigit Carry is loaded from bit 6 of the old register value.

Affected flags: CC, C (if WC), IDC (if WC)

rrl - Rotate Register Left

These instructions perform a left-rotate on the specified register in-place. The exact operation depends on the state of the WC flag in the PSL.

If WC is clear, the register is left-rotated and the Carry and Interdigit Carry are not changed. Bit 0 of the new register value is set from Bit 7 of the previous value.

If WC is set, the register is left-rotated through the Carry. The previous Carry is shifted into bi t 0 of the result and the previous bit 7 becomes the next Carry. Additionally, the Interdigit Carry is loaded from bit 4 of the old register value.

Affected flags: CC, C (if WC), IDC (if WC)

dar - Decimal Adjust Register

These instructions perform a decimal adjust based on the states of the Carry and Interdigit Carry to help perform arithmatic on packed BCD values.

If the Carry is clear, a value of A0h is added to the register’s value.

If the Interdigit Carry is clear, a value of 0Ah is added to the register’s value.

If both are clear, a value of AAh is added to the register’s value.

Packed BCD operations may then be performed according to these algorithms:

To perform addition, add 66h to either term, then add both terms. This instruction will then adjust the sum to its correct BCD value.

To perform subtraction, perform subtraction as normal, then execute this instruction to get the correct BCD result.

Affected flags: none

wrtc - Write Command

This instruction triggers a external IO Write transaction using the value of the specified register as the value written. The IOC and WE lines are asserted as part of the transaction.

Affected flags: none

wrtd - Write Data

This instruction triggers a external IO Write transaction using the value of the specified register as the value written. The IOD and WE lines are asserted as part of the transaction.

Affected flags: none

redc - Read Command

This instruction triggers a external IO Read transaction and saves the received value into the specified register. The IOC and OE lines are asserted as part of the transaction.

Affected flags: CC

redd - Read Data

This instruction triggers a external IO Read transaction and saves the received value into the specified register. The IOD and OE lines are asserted as part of the transaction.

Affected flags: CC

wrte - Write Extended IO

This instruction triggers a write to an on-die IO device using the value of the specified register. A immediate 8-bit address follows the opcode which is decoded to address one of the on-die peripheral registers.

Affected flags: none

rede - Read Extended IO

This instruction triggers a read from an on-die IO device and writes the received value into the specified register. A immediate 8-bit address follows the opcode which is decoded to address one of the on-die perhipheral registers.

Affected flags: CC

spsu - Store Program Status Upper

This instruction copies the value of the PSU into R0. Flags are not affected until after the copy.

Affected flags: CC

spsl - Store Program Status Lower

This instruction copies the value of the PSL into R0. Flags are not affected until after the copy.

Affected flags: CC

lpsu - Load Program Status Upper

This instruction copies the value in R0 into the PSU.

Affected flags: S, F, II, SP

lpsl - Load Program Status Lower

This instruction copies the value in R0 into the PSL.

Affected flags: CC, IDC, RS, WC, OVF, COM, C

halt - Halt

This instruction pauses program execution until an interrupt occurs. The Program Counter will become stuck in place until the servicing of an interrupt routine. Once the interrupt routine returns, execution resumes from the first instruction following the halt.

Affected flags: none

cpsu - Clear bits in Program Status Upper

This immediate-addressed instruction clears specific bits in the PSU according to the mask in its immediate argument. All bits in the PSU for which the corresponding bit in the mask is a one will be cleared to zero.

Affected flags: S, F, II, SP

cpsl - Clear bits in Program Status Lower

This immediate-addressed instruction clears specific bits in the PSL according to the mask in its immediate argument. All bits in the PSL for which the corresponding bit in the mask is a one will be cleared to zero.

Affected flags: CC, IDC, RS, WC, OVF, COM, C

ppsu - Preset bits in Program Status Upper

This immediate-addressed instruction sets specific bits in the PSU according to the mask in its immediate argument. The mask is simply inclusive-OR’d onto the PSU.

Affected flags: S, F, II, SP

ppsl - Preset bits in Program Status Lower

This immediate-addressed instruction sets specific bits in the PSL according to the mask in its immediate argument. The mask is simply inclusive-OR’d onto the PSL.

Affected flags: CC, IDC, RS, WC, OVF, COM, C

tpsu - Test Program Status Upper

This immediate-addressed instruction tests bits in the PSU according to the mask in its immediate argument. Every bit in the PSU for which there is a one in the mask is checked. The test succeeds if all checked bits are one.

Affected flags: CC

tpsl - Test Program Status Lower

This immediate-addressed instruction tests bits in the PSL according to the mask in its immediate argument. Every bit in the PSL for which there is a one in the mask is checked. The test succeeds if all checked bits are one.

Affected flags: CC

nop - No Operation

No operation is performed and the following instruction executed.

Affected flags: none

tmi - Test Under Mask Immediate

This immediate-addressed instruction tests bits in the value of the specified register according to the mask in its immediate argument. Every bit in the register value for which there is a one in the mask is checked. The test succeeds if all checked bits are ones.

Affected flags: CC

zbrr - Zero-Branch Relative

This relative-addressed instruction performs a unconditional branch to a location relative to page 0, byte 0. The displacement in the argument is interpreted as being relative to this address and negative values cause a wrap-around to page 0, byte 8191 - 8128.

Affected flags: CC

zbsr - Zero-Branch to Subroutine Relative

This instruction behaves identically to zbrr explained above, except that it additionally pushes a return address onto the internal stack. This address is a complete Instruction Pointer and will always point to the instruction immediatly following the branch.

Affected flags: CC

bxa - Branch Indexed, Absolute

This absolute-addressed instruction is encoded the same as an unconditionally, absolute branch instruction but has indexing implicitely enabled. The index register is always R3, however.

Affected flags: CC

bsxa - Branch to Subroutine Indexed, Absolute

This instruction behaves identically to bxa explained above, except that it additionally pushes a return address onto the internal stack. This address is a complete Instruction Pointer and will always point to the instruction immediatly following the branch.

Affected flags: CC

push - Push to Internal Stack

This instruction pushes a 16-bit wide value pair onto the internal stack. These values are taken from registers R0 (LSB, bits 0 - 7) and R1 (MSB, bits 8 - 15).

Affected flags: none

pop - Pop from Internal Stack

This instruction pops a 16-bit wide value pair from the internal stack into registers R0 (LSB, bits 0 - 7) and R1 (MSB, bits 8 - 15). No flags are affected despite the register writes.

push and pop are intended to allow the call stack to be spilled over into memory if necesarry and are not meant to be used to store program data.

Affected flags: none

mul - Unsigned multiply of R0 and R1

This instruction multiplies the value of R0 by the value of R1. This produces a 16-bit result that is written back into R0 (LSB, bits 0 - 7) and R1 (MSB, bits 8 - 15). The Condition Code is set according to the full 16-bit value.

Affected flags: CC

xchg - Exchange R0 and R1

This instruction exchanges the values in R0 and R1 in-place without affecting flags.

Affected flags: none

clr - Clear Register

This instruction sets the value of the specified register to zero. No flags are affected despite the register change.

Affected flags: none

trap - Software Trap

This instruction sets the trap interrupt (priority 4) as pending. This does not mean that the interrupt is immediately served as any incoming higher-priority interrupts will be served first. Additionally, the instruction has no effect if the global Interrupt Inhibit flag is set. The trap will remain pending until the flag is cleared.

Affected flags: none

clrt - Clear Trap Pending Flag

This instruction serves as the pending interrupt clear for the software trap. It will always clear any pending trap interrupt even if that interrupt hasn’t been served yet.

Affected flags: none

cpl - Complement Register

This instruction complements all the bits of the specified register’s value. Notably, this operation does not affect any flags.

Affected flags: none

pshs - Push Program Status

This instruction pushes the whole PSW onto the internal stack. It is meant to only be used at the start of interrupt routines.

Affected flags: none

pops - Pop Program Status

This instruction pops a value from the internal stack and loads it into the PSW. It is meant to only be used at the end of interrupt routines.

Affected flags: S, F, II, SP, CC, IDC, RS, WC, OVF, COM, C

svb - Set Interrupt Vector Base

This instruction sets the value of the IVB register by copying the combined value of R0 (LSB, bits 4 - 7) and R1 (MSB, bits 8 - 15). Bits 0 - 3 are always zero.

Affected flags: none

lodf - Load Register value, Far

This instruction performs a register load from memory same as lodr/loda, but using Far Addressing.

Affected flags: CC

ldfi - Load Register value, Far Indirect

This instruction performs a register load from memory same as lodr/loda but using Far Addressing plus Indirect Addressing.

Affected flags: CC

strf - Store Register value, Far

This instruction performs a register store to memory same as strr/stra, but using Far Addressing.

Affected flags: none

stfi - Store Register value, Far Indirect

This instruction performs a register store to memory same as strr/stra, but using Far Addressing plus Indirect Addressing.

Affected flags: none

bctf - Branch on Condition True, Far

This instruction behaves the same as bcta, branching only if the Condition Code value matches the Mask in the opcode, but using Far Addressing. This sets all 3 bits of Page Control as well as all 13 bits of the Program Counter.

Affected flags: none

bstf - Branch to Subroutine on Condition True, Far

This instruction behaves the same as bctf, except that it additionally pushes a return address onto the internal stack if the branch is taken. This address is a complete Instruction Pointer and will always point to the instruction immediatly following the branch.

Affected flags: none

brnf - Branch on Not Zero, Far

This instruction behaves the same as brna, branching only if the specified register’s value is not zero, but using Far Addressing. This sets all 3 bits of Page Control as well as all 13 bits of the Program Counter.

Affected flags: none

bsnf - Branch to Subroutine on Not Zero, Far

This instruction behaves the same as brnf, except that it additionally pushes a return address onto the internal stack if the branch is taken. This address is a complete Instruction Pointer and will always point to the instruction immediatly following the branch.

Affected flags: none

bcff - Branch on Condition False, Far

This instruction behaves the same as bcfa, branching only if the Condition Code does not match the Mask in the opcode, but using Far Addressing. This sets all 3 bits of Page Control as well as all 13 bits of the Program Counter.

The CC mask may not be equal to 3. This opcode is used by another instruction.

Affected flags: none

bsff - Branch to Subroutine on Condition False, Far

This instruction behaves the same as bcff, except that it additionally pushes a return address onto the internal stack if the branch is taken. This address is a complete Instruction Pointer and will always point to the instruction immediatly following the branch.

The CC mask may not be equal to 3. This opcode is used by another instruction.

Affected flags: none

birf - Branch on Incrementing Register Not Zero, Far

This instruction behaves the same as bira, branching only if the value of the specified register after it is incremented is not zero, but using Far Addressing. This sets all 3 bits of Page Control as well as all 13 bits of the Program Counter.

Affected flags: none

bdrf - Branch on Decrementing Register Not Zero, Far

This instruction behaves the same as bira, branching only if the value of the specified register after it is decremented is not zero, but using Far Addressing. This sets all 3 bits of Page Control as well as all 13 bits of the Program Counter.

Affected flags: none