CI2406 Multi-Project Die

Overview

• Multiplexer
  • I/O Routing and design selection
  • Custom Settings Register
  • Wishbone address map
  • Design address map
  • Project Selection Register
• Z80
  • Pinout
• MOS6502
  • Pinout
  • Custom Settings
• AS1802
  • Pinout
  • Memory Bus
  • Extended Instructions
    • SWAP
    • CMHI
    • LMHI
    • GMHI
    • PXN
    • DBNZ
    • MUL
    • MLI
    • DIV
    • DVI
    • MOD
    • MDI
  • Custom Settings
• S8X305
  • Pinout
  • Spiflash Interface
  • Built-in IO and RAM
• ScrapCPU
  • Pinout
  • Spiflash Interface
  • Programming Model
    • Registers
    • Addressing Modes
    • Quick Mode
  • Original Instruction Set
    • LDA - Load A
    • STA - Store A
    • STB - Store B
    • LDP - Load P
    • LDM - Load MAR
    • LDI - Load Immediate
    • ADD - Add
    • ADC - Add with Carry
    • SUB - Subtract
    • SBC - Subtract with Carry
    • EQL - Equality Comparison
    • MAG - Magnitude Comparison
    • JMP - Jump unconditionally
    • JZ - Jump if Zero
    • JNZ - Jump if Not Zero
  • Extended Instruction Set
    • XOR - Logic Exclusive-OR
    • AND - Logic AND
    • RSH - Right Shift
    • RSHC - Right Shift with Carry
    • JC - Jump if Carry
    • SEC - Set Carry
    • CLC - Clear Carry
    • IRET - Return from Interrupt
    • TC - Toggle Compatibility
  • Compatibility Mode
  • Incompatibilities
  • IO Ports
  • Interrupt
• VLIW
  • Pinout
  • Memory Bus
  • Instruction Cache
  • Programming Model
  • Instruction Set Architecture
    • No-op
    • ALU-Type
    • Immediate-Type
    • Loadstore-Type
    • Jump-Type
    • Branch-Type
    • Predicate-Type
    • Predicates
    • Breaks
    • Limitations
  • IO-Block
    • Timers
    • Serial Ports
    • GPIO Port
    • Cache Enable
    • Alternate Function Control
    • PWM
    • Cache Hit Counter
  • Interrupts
  • Custom Settings
• FG Cap Test
  • Pinout