wafer.space Multi-Project Die

Overview

• Multiplexer
  • I/O Routing and design selection
  • Design address map
• TinyTapeout VGA Demos
  • Pad Assignments
• 24-bit color VGA demo
  • Pad Assignments
• Miscelaneous
  • Pad Assignments
• Nanoprocessor Replica
  • Pad Assignments
  • Bus cycles
  • Direct Control Port
  • Interrupts
  • Programming Model
  • Instruction Set
    • SBS - Skip on Bit Set
    • SBZ - Skip on Bit Zero
    • SBN - Set Bit N
    • CBN - Clear Bit N
    • INB - Increment Binary
    • IND - Increment Decimal
    • DEB - Decrement Binary
    • DED - Decrement Decimal
    • CLA - Clear Accumulator
    • CMA - Complement Accumulator
    • LSA - Left-Shift Accumulator
    • RSA - Right-Shift Accumulator
    • SES - Skip on Extend Set
    • SEZ - Skip on Extend Zero
    • LDR - Load ROM Data
    • LDA - Load Accumulator
    • STA - Store Accumulator
    • LDI - Load Indexed
    • STI - Store Indexed
    • STR - Store ROM Data
    • STE - Set Extend
    • CLE - Clear Extend
    • DSI - Disable Interrupt
    • ENI - Enable Interrupt
    • SLT - Skip on Less Than
    • SEQ - Skip on Equal
    • SAZ - Skip on Accumulator Zero
    • SLE - Skip on Less Equal
    • SGE - Skip on Greater Equal
    • SNE - Skip on Not Equal
    • SAN - Skip on Accumulator Not zero
    • SGT - Skip on Greater Than
    • INA - Input Data to Accumulator
    • OTA - Output Accumulator
    • OTR - Output ROM data
    • STC - Set Control
    • CLC - Clear Control
    • SFS - Skip on Flag Set
    • SFZ - Skip on Flag Zero
    • RTI - Return from Interrupt
    • RTE - Return w. Enable
    • NOP - No Operation
    • JAI - Jump through Accumulator Indirect
    • JAS - Jump through Accumulator indirect to Subroutine
    • JMP - Jump
    • JSB - Jump to Subroutine
    • RTS - Return from Subroutine
    • RSE - Return from Subroutine and Enable
• Simple CPU
  • Pad Assignments
  • Programming Model
  • Loader Operation
  • CPU Instructions
    • NOT - NOT accumulator
    • SUBm - Substract Memory
    • ADDm - Add Memory
    • ORm - OR Memory
    • STOREm - Store to memory
    • BZ - Branch if Zero
    • ANDm - AND Memory
    • LOADm - Load from Memory
    • IN - Input from IO
    • SUBi - Substract Immediate
    • ADDi - Add Immediate
    • ORm - OR Memory
    • OUT - Output to IO
    • BR - Branch unconditionally
    • ANDi - AND Immediate
    • LOADi - Load Immediate
• AS65RV32
  • Pad Assignments
  • Intended Pinouts
    • DIP-40 Pinout for 6502 pad-out
    • DIP-40 Pinout for 6510 pad-out
  • Bus Interface
    • Basic Bus Cycle
    • Effect of “Half write cycle” low
    • Successive writes
    • Reset/Vector Fetch Sequence
  • Peripherals
    • GPIO Port
    • UART
    • Interrupt-capable timer
  • Pseudo-RNG
  • Standard CSRs
  • cpuconf CSR
  • Interrupts / Traps
  • Non-Maskable Interrupt
• SID 2 (SID-compatible FM-Synthesizer)
  • Pad Assignments
  • Registers
    • Bank 0
    • Bank 1
  • Functional Description
    • Compatibility Mode
    • Additive Synthesis
    • Frequency Modulation Synthesis
    • Sine Wave Generation
• NTSC Test
  • Pad Assignments
• DRAM Controller
  • Pad Assignments
  • Intended Pinout
  • Configuration
  • Memory access function
• GPIO Chip
  • Pad Assignments
  • Bus Interface
  • Register Descriptions
    • GPIO Port
    • Serial Ports
    • Timer/Counters
    • Digital To Analog Converters
    • PRNG
    • General-Purpose Registers
  • Interrupts
• SID
  • Pad Assignments
• AS65C02/AS65C10
  • Pad Assignments
  • Intended Pinouts
    • DIP-40 Pinout for 6502 pad-out
    • DIP-40 Pinout for 6510 pad-out
  • “Detect” Instruction
  • Additional Instructions
    • SEV - Set V
    • MUL - Multiply
    • CHRP - Chirp
    • COR - Corrupt
    • EXTEND - Reserved
• Commodore 64 PLA
  • Pad Assignments
  • Intended Pinout