Multiplexer

I/O Routing and design selection

Every design has access to up to 42 bi-directional I/O lines with a 24mA drive strength. To accomplish this, the bidir[41:0] pad signals are routed to the designs as follows:

• All designs directly read from bidir_PAD2CORE or io_in_buffered

• Two sets of wires, io_out_[design_name] and io_oe_[design_name] leave each design and are routed into the Multiplexer

• As the name implies, the Multiplexer only passes one set of io outs and output enables to the chip pads’ bidir_CORE2PAD and bidir_CORE2PAD_OE

• bidir_CORE2PAD_IE is automatically generated by inverting bidir_CORE2PAD_OE

• For each design, the Multiplexer provides a fixed config for bidir_CORE2PAD_SL, bidir_CORE2PAD_PU, bidir_CORE2PAD_PD and bidir_CORE2PAD_CS

Additionally, all non-selected designs are held perpetually in reset to minimize dynamic power consumption.

To reduce fan-out at bidir_PAD2CORE, a “InputRepeater” macro exists on the die, consisting only of buffers which repeat bidir_PAD2CORE into io_in_buffered. As this creates additional input delay, some performance-critical designs still sample bidir_PAD2CORE directly. Designs where clock rate is of no special concern make use of io_in_buffered.

Design address map

Note that all design selection pads have internal pull-ups. For cases where project selection is to be hard-wired, a “0” corresponds to a bonded pad and a “1” corresponds to a floating pad.